Job Description
Job Title:Timing Constraint Development for SynthesisLocation: RemoteDuration: 12 MonthsJob Description:We are seeking an experienced professional to join our remote team for Timing Constraint Development for Synthesis.Responsibilities:Develop micro-architecture specifications for SoC design blocks.Contribute to multiple SoC projects.Review SoC Chip Architecture specifications.Collaborate with SoC integration, verification, and physical design teams, as well as IP vendors.Oversee complete block development from specifications to synthesis/STA.Contribute to innovative SoC projects.Collaborate with industry experts.Education and Experience:Extensive experience in micro-architecture design for SoC sub-blocks.Proficient in SoC RTL coding (Verilog or System-Verilog).Skilled in RTL Code Linting and CDC checks.Strong knowledge of AXI/AHB bus protocols, GigBE, USB, NAND Flash, PCIe Gen2/3, DDR2/3.Preferred experience in PCIe and HBM memory protocols.Experience in low power and DFx design techniques is a plus.Skills:Micro-architectureSoC designSoC RTL codingRTL Code LintingRTL integrationLow power designPCIe and HBM memory protocolsIntellectt
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